1. Field of the Invention
The present invention relates to an image processing apparatus, more specifically, to an image processing apparatus for producing display image data of the Phase Alternating by Line (PAL) system from a coded image signal of the National Television System Committee (NTSC) system compressed by using the system of Moving Picture Experts Group (MPEG).
2. Description of the Related Art
In the image signal specified by either the NTSC system or PAL system, the frame rate is different in the both cases: NTSC system has 30 frames/sec. or strictly 29.97 frames/sec., while PAL system has 25 frames/sec. For this reason, a frame rate transformation is required in the case of displaying the image signal of PAL system in response to the image signal coded by NTSC system.
FIG. 5 is an electrical block diagram showing an MPEG-decoded image processing apparatus having a transformation function of frame rate to be transformed from the NTSC system to PAL system, for explaining a related art. FIG. 6 is a flow chart explaining an operation of the image processing apparatus in the decoding. FIG. 7 is a flow chart explaining an operation of the image processing apparatus in the display. FIGS. 8(a), 8(b) and 8(c) are explanatory diagrams for explaining the frame rate transformation by the image processing apparatus.
As shown in FIG. 5, the MPEG-decode image processing apparatus having the transformation function of frame rate to be transformed the NTSC system to PAL system, constitutes substantially an input buffer 101, a variable length decoder 102, a reverse quantizing part 103, a reverse discrete cosine transformation (DCT) part 104, a motion compensating part 105, an image memory 116 having a first core-picture memory 106, a second core-picture memory 107, a B-picture memory 108 and a switching part 109. The apparatus also includes an aspect ratio transforming filter 110, a PAL synchronizing signal generator 111, a decoding controller 112, a skipped image deciding part 113, a memory controller 114 and a display controller 115.
According to such constitution, the input buffer 101 stores temporarily a coded image input signal supplied from a coded image signal supply end. The variable length decoder 102 decodes the coded image input signal having variable length codes. The reverse quantizing part 103 quantizes reversely the decoded signal that has been quantized at the coded signal supply end. The reverse DCT part 104 reversely transforms the decoded signal that has also been transformed as discrete cosine transformation (DCT) at the coded signal supply end. The motion compensating part 105 adds the decoded image signal to an image reference signal in correspondence with a process such that an image signal is coded by a difference from the image reference signal at the coded signal supply end. The first core-picture memory 106 and second core-picture memory 107 each receives a core picture (I-picture or P-picture) alternately and outputs it therefrom. The B-picture memory 108 holds a B-picture itself. The switching part 109 selects either one of the core picture from the first and second core-picture memories 106 and 107 or the B-picture from the B-picture memory 108, and outputs the one of those. As is apparent from the constitution, the image memory 116 has the first and second core-picture memories 106 and 107, the B-picture memory 108, and the switching part 109.
The aspect ratio transforming filter 110 transforms an aspect ratio of an output image data from the image memory 116. The PAL synchronizing signal generator 111 generates a synchronizing signal for controlling a timing between the decoding operation and display operation in PAL system. The decoding controller 112 controls the decoding operation to be performed in the necessary components in response to the synchronizing signal of the PAL system output from the PAL synchronizing signal generator 111. The skipped image deciding part 113 decides a frame to be skipped and instructs so as to control the frame to the decoding controller 112 for a purpose of transformation between the NYSC and PAL system.
The memory controller 114 controls the image data being stored in the image memory 116 in response to an instruction from the decoding controller 112, and also controls to read the image data from the image memory 116 in response to an instruction from the display controller 115. The display controller 115 controls the read operation of the image memory 116 controlled by the memory controller 114 in response to the synchronizing signal from the PAL synchronizing signal generator 111, and also controls the operation of the aspect ratio transformation performed in the aspect ratio transforming filter 110.
Referring to FIGS. 5 to 8, the operation of frame rate transformation from the NTSC system to PAL system will be described below as a related art. First, an image transmission manner specified by MPEG system in general will be explained. In the case of MPEG system, the image transmission is carried out by using three types of image data containing an I-coded data, P-coded data and B-coded data at every predetermined number of frames dependent on original image data. Specifically, the I-coded data is image data coded at one frame and completed within one image data. The decoded I-coded data is referred to as an I-picture. The P-coded data is image data coded by a difference extracted from a reference of image data which is previously generated from either the I-coded data or P-coded data. The image data decoded by adding the difference data obtained from decoding the P-coded data to the reference image data, is referred to as a P-picture. The B-coded data is image data coded by a difference extracted from a reference of image data that is generated from either the immediately preceding and succeeding I-coded data or the P-coded data. The image data decoded by adding a difference data obtained from decoding the B-coded data to the reference image is referred to as a B-picture.
The image processing apparatus shown in FIG. 5 transforms the frame rate from NTSC system to PAL system with the B-picture skipped and displayed in the ratio of one field to six frames when a coded image input signal is decoded in PAL system.
Referring to FIGS. 5 and 6, the decoding operation by the image processing apparatus will be described below. The decoding operation is first carried out by the decoding controller 112 controlling the necessary components in response to the synchronizing signal of PAL system output from the PAL synchronizing signal generator 111.
That is, the coded image input signal containing variable length codes of the NTSC system is held in the input buffer 101, thereafter, it is decoded in the variable length decoder 102. At this time, a frame to be skipped is decided by the skipped image deciding part 113, and the skip of B-picture is carried out at the time of the decoding performed in the variable length decoder 102 with the decoding controller 112 controlled. The variable length decoded signal is reversely quantized in the reverse quantizing part 103, and transformed as a reverse discrete cosine transformation by the reverse DCT part 104. Afterward, either the I-picture or P-picture output from the motion compensating part 105 is alternately written into the first and second core-picture memories 106 and 107 and the B-picture is written into the B-picture memory 108, in response to the control by the memory controller 114, terminating the decoding of one frame.
The subsequent operation will be explained with a flow chart shown in FIG. 6. A decode-starting position on the frame specified by PAL system is detected at the time of termination of decoding a previous frame in step Q1. Afterward, if five frames or more are decoded in step Q2, the decoded image signal is confirmed as a B-picture in step Q3 and one frame is skipped in step Q4. It is noted that the one frame is not skipped if neither five frames or more are decoded nor the decoded image signal is a B-picture. The decoding operation is then started in step Q5 to terminate the decoding for one frame in step Q6. Such operation described above is repeatedly carried out until the decoding for all coded image input signals is terminated in step Q7.
Referring to FIGS. 5 and 7, the display operation by the image processing apparatus will be explained below. The display operation is basically carried out by the display controller 115 which controls the necessary components in response to the synchronizing signal having a frequency predetermined by the PAL system output from the PAL synchronizing signal generator 111.
In the case of displaying the image data stored in the image memory 116, it is in turn read out from the first core-picture memory 106, the core-picture memory 107 and the B-picture memory 108 in accordance with the predetermined order and displayed with the switching part 109 switched.
The subsequent operation of the display will be explained with reference to FIG. 7. A display starting position of the frame specified by PAL system is detected at the time of terminating the display of the previous frame in step R1. The display for frame begins in step R2 and is confirmed whether the display for one frame is terminated in step R3. Such operation described above is repeatedly carried out until the display for all frames is terminated in step R4. The aspect ratio transforming filter 110 then transforms the aspect ratio of the image data output from the switching part 109, as required, to obtain a desirable display image data.
FIGS. 8(a), 8(b) and 8(c) are explanatory diagrams showing differences of display pictures specified by NTSC system and PAL system in the case of using the conventional frame rate transformation. In the drawings, both a top and bottom field constituting one frame picture are indicated by numerals plus lower case suffix characters xe2x80x9cTxe2x80x9d and xe2x80x9cBxe2x80x9d, respectively. Now, a case where coded core pictures I00T and I00B are present in a following frame having core pictures P14T and P14B will be explained below. Conventionally, the frame rate transformation is carried out by skipping at every six frames of the decoded image signal, and the read of a B-picture positioned on the last one frame is indicated by a regular dotted pattern, as shown in FIG. 8(a).
That is, in the case of outputting a decoded image signal specified by the NTSC system, six frames are outputted as display picture output as shown in FIG. 8(b). In the case of carrying out the frame rate transformation in PAL system, the B-pictures B05T and B05B in one frame out of six shown in FIG. 8(a) is skipped to read and five frames are outputted alone as shown in FIG. 8(c).
According to the image processing apparatus, one frame is skipped to read at every six frames of the decoded image signal specified by NTSC system and the decoded image signal is displayed as picture specified by PAL system. This causes frame loss to display unnatural picture that gives viewers incongruity. Also, in the case where the B-picture is not used for the coding system, it is unable to carry out the frame rate transformation.
It is therefore an object of the present invention to provide an image processing apparatus capable of carrying out a frame rate transformation without having a B-picture in a coded image signal, in the case where the apparatus produces display image data of PAL system from the coded image input signal specified by NTSC system.
According to a first aspect of the present invention, there is provided an image processing apparatus, including that a coded image input signal specified by NTSC system is decoded by the frame rate of NTSC system and written into an image memory. The written image data is then read out by the frame rate specified by PAL system from the image memory and displayed on a screen, constituting the image processing apparatus to carry out a frame rate transformation from NTSC system to PAL system.
According to a second aspect of the present invention, there is provided an image processing apparatus, including that a coded image input signal of the MPEG specified by NTSC system is decoded by the frame rate of NTSC system. The decoded image signal of MPEG is then written into an image memory. The image data written in the image memory is read out with the frame rate of PAL system and displayed on a screen, constituting the image processing apparatus to carry out a frame rate transformation from the NTSC system to PAL system with the image data culled at every field.
According to a third aspect of the present invention, there is provided an image processing apparatus, wherein the apparatus includes first synchronizing signal generating means which generates a synchronizing signal of the NTSC system; second synchronizing signal generating means which generates a synchronizing signal of the PAL system; decoding means operated by the synchronizing signal of NTSC system to decode the coded image input signal of MPEG specified by the NTSC system and restore image data; and an image memory stored the restored image data in response to the synchronizing signal of NTSC system and supplied the image data to be displayed on a screen in response to the synchronizing signal of PAL system.
The image memory may include two core-picture memories to store and supply alternately core pictures having an I-picture and P-picture, respectively, and also include a B-picture memory to store and supply B-picture. In addition to such constitution, a memory controller is also connected to the image memory which stores the image data in response to the synchronizing signal of NTSC system and supplies the image data in response to the synchronizing signal of PAL system. The memory controller performs such that when a state of the supplied image data to be outstripped the stored image data is predicted at one core-picture memory, the image data from starting to read a field is read out from the other core-picture memory which is switched from the one core-picture memory. Also, when a state of the supplied image data to be outstripped the stored image data is predicted at the B-picture memory, the stored image data with non-updated data remained is read out continuously.
The image processing apparatus may be constituted such that when the image data read out from the image memory to be displayed it on the screen is inverted such that a top field is as bottom in the order, or the other way around, such image mutilation caused by the inverted line may be corrected by filtering the image data through an inverted line correcting filter.
The inverted line correcting filter may be constituted such that when the image data of a top field is displayed as a bottom field, a mean value data is produced from the image data of the present line and that of one succeeding line, and supplied to a next stage. When the image data of the bottom field is displayed as a top field, a mean value data is produced from the image data of present line and that of one preceding line and supplied to the next stage. When either the image data of the top field is displayed as a top field or the image data of the bottom field is displayed as a bottom field, a mean value data is produced from multiplying the image data of the present line, the image data of one preceding line and the image data of one succeeding line by a predetermined coefficient, respectively, and supplied to the next stage.
According to such constitution describe above, the decoding system operates in synchronism with a timing of the NTSC system to write decoded image signal in the image memory while the display system operates in synchronism with a timing of the PAL system to read the decoded image data from the image memory and display it on the screen. At this time, the output image data of PAL system becomes image data with data outputted in the NTSC system when starting to output the fields specified by the PAL system. In the case where the decoded image signal is written in a memory bank but the display image data is read from the same memory bank, and also the case where display image data to be outstripped the decoded image signal is predicted with a core picture displayed in relation to one core-picture memory, image data being stored in a memory bank of the other core-picture memory is supplied. In the case where the display outstrips the decoding with the B-picture displayed, output image data is switched from the image signal being decoded to the image data previously decoded during the display. As a result from such display, when a top field is inverted to a bottom field in the output order within one frame, an image multilation is corrected by filtering the image data through the inverted line correcting filter.
Accordingly, since the five out of six fields decoded are displayed on the screen, the frame rate transformation is achieved from the NTSC system to PAL system. At this time, the skipping for display is carried out at every one extent field, therefore, unnatural displayed image becomes reduced thereby viewers do not have incongruity caused by the displayed image in comparison with one extent frame skipped conventionally. In addition, since all coded image input data are decoded and the display is skipped alone, the frame rate transformation can be performed even though the coded image input data does not contain the B-picture.